We’re pleased to offer two new webinars in September that will provide techniques to speed up PCB routing time.
Webinar #1; September 12
Accelerating PCB Routing by Optimizing FPGA Pin Assignments
Attend our September 12 webinar to learn how you can accelerate routing and reduce PCB layer counts by optimizing FPGA pin assignments during layout.
When: 17:00 to 18:00 CET
Ideal for PCB, hardware, and FPGA designers, this hour-long session will highlight the capabilities of Cadence® Allegro® FPGA System Planner and Cadence Allegro PCB Editor. You’ll learn:
- How to identify FPGA pins that need to be swapped, using Allegro PCB Editor
- How to shorten the time to route signals to FPGAs and potentially reduce the number of layers on your PCB, using Allegro FPGA System Planner as an engine inside Allegro PCB Editor
Webinar #2: September 18
Routing Interfaces Quickly and Efficiently on PCBs Part 2
To continue sharpening your routing expertise, attend Part 2 of our webinar, “Routing Interfaces Quickly and Efficiently on PCBs.”
When: 17:00 to 18:00 CET -or- 6:00pm to 7:00 pm PDT
Ideal for PCB designers and ECAD managers, this webinar will provide techniques on accelerating routing of high-speed interfaces like DDRx, PCI Express, and SATA using new auto-interactive and improved interactive routing technology in the Cadence® Allegro® PCB Designer solution. Part 1 is available as an archived session.
In Part 2, you’ll learn:
- When to use interactive and new auto-interactive capabilities to plan, route, and tune your signals
- How you can use newly released Auto-interactive Breakout Technology (AiBT) to shorten the time to route interfaces to high pin count BGAs and possibly reduce the number of layers required on your PCB
- How to use newly released add connect by scribbling a path on the canvas and let the route engine create an accurate path based on your guidance